1. Field of the Invention
The present invention relates to electrical circuit components, and more particularly the present invention relates to a two-terminal, low capacitance barrier controlled transient voltage suppression (TVS) semiconductor diode device.
2. Introduction to the Invention
The need to protect electronic circuits and components against over-voltage conditions is well known. In particular, semiconductor devices include structural elements and regions, such as base or gate regions that may be damaged or destroyed if an energy pulse in excess of a maximum voltage rating is permitted to reach the device. Yet, there are several trends emerging that make over-voltage circuit protection ever more challenging. One trend is toward faster data rates. Faster data rates require that protection devices present lower and lower loading impedance, particularly capacitive reactance, at the point of protection of the protected circuit, usually a data or control input base or gate of a semiconductor circuit element.
A second trend is toward circuitry operating at lower voltages, with a pronounced trend from 5-volt logic to 2.8-volt logic and even lower voltages. This trend requires that integrated circuits (“IC”) be made with ever-smaller physical features. By reducing IC feature size, increased speeds are achieved. By reducing the voltage, the power dissipated per circuit element is also reduced. Yet, by having smaller feature size, more logic circuit elements are typically included within the overall IC device design; and, with higher data rates, more overall current is required. Thus, the trends to lower feature size and lower voltages combine to result in a net increase in overall current flow through the resultant IC.
One difficulty in protecting ICs has been to realize over voltage protection devices that limit the voltage surge to a predetermined low voltage value or “clamp voltage”. Yet another difficulty has been to provide a protection device that presents a relatively low shunt capacitance to the low voltage circuit being protected and that is relatively simple and therefore can be made at relatively low cost.
There are several established approaches to protect electronic circuitry against over-voltage. One approach is to use a simple PN junction diode. For the typical PN silicon diode, the forward conduction voltage is about 0.6 volts. (By forward conduction voltage is meant the forward bias voltage level across the diode at which the current begins dramatically to increase relative to the current previously observed at lower voltages close to the forward conduction voltage. The forward conduction voltage is used herein synonymously with “clamping” voltage.) By putting a single PN junction silicon diode in parallel across an input terminal of a device or element to be protected, a forward bias clamping voltage typically of about 0.6 volts is obtained. In metal-semiconductor junction diodes (Schottky diodes) the forward bias clamping voltage is typically 0.3 volts. Bipolar protection may be achieved by placing two diodes in a back-to-back parallel connection configuration. One well-known drawback of PN junction diodes is that the diode presents a non-linear electrical capacitive reactance at the input of the protected device, with maximum parasitic capacitance typically presented at lowest input potential. The other obvious drawback of the conventional PN junction diode is that it is effective to protect only those signal levels that are below its intrinsic forward conduction voltage, levels that are simply too low for even the low voltage IC circuitry now widely proliferating. A circuit designer could also add plural forward-biased diodes in series as one way of increasing forward conduction voltage and protecting against over voltage surges, whether from ESD or other sources, but, as in the case of single diodes, the I-V characteristics are not very sharp, and therefore the clamping voltage varies significantly with diode forward current, and in a relatively high percentage of cases, with changes in diode temperature.
In order to overcome the fixed low voltage limitations of ordinary PN junction diodes, or metal-semiconductor diodes, designers have also used reverse-biased “Zener” diodes and “avalanche” diodes, either singly or in back-to-back series connection configuration. Zener diodes are made in such a way that their reverse breakdown voltage may be controlled from slightly more than one volt to approximately seven volts. Avalanche diodes are made with reverse breakdown voltages from approximately seven volts to hundreds of volts. Yet, the problem of relatively high parasitic capacitance remains with zener diodes and with avalanche diodes.
Alternatively, relatively complex semiconductor structures known as “transient voltage suppression” (TVS) diodes have been proposed. Two main categories of TVS diodes are well known: avalanche and “punch-through”. One example of a punch-through TVS diode is set forth in U.S. Pat. No. 6,015,999 to Yu et al., entitled: “Low-voltage punch-through transient suppressor employing a dual-base structure”. Processing of the requisite NPPN multi-layer devices requires relatively expensive, very high resistivity epitaxy and formation of precisely controlled doping gradients during fabrication in order to function as described. These prior devices are therefore complex and costly to make.
A commercial product including an example of the NPPN TVS diode is described in a data sheet entitled “SEMTECH SLVU2.8-8 EPD TVS™ Diode Array for ESD and Latch-Up Protection”. Although the device thus described is complex, not easily made and therefore expensive, it does manifest a controllable threshold voltage, desirable I-V characteristics and relatively low loading capacitance. Other U.S. patents relating to punch-through diodes include U.S. Pat. No. 6,602,769 to Einthoven et al.; U.S. Pat. No. 6,600,204 to Einthoven et al.; U.S. Pat. No. 6,597,052 to Hurkx et al.; U.S. Pat. No. 6,489,660 to Einthoven et al.; U.S. Pat. No. 6,392,266 to Robb et al.; U.S. Pat. No. 5,880,511 to Yu et al.; and U.S. Pat. No. 4,405,932 to Ishii et al. Punch-through diodes typically have a PN junction with one side being relatively thin (approximately 1 μm through 5 μm) and of high resistivity (approximately 100 Ω-cm). Low capacitance is achieved as the entire high resistivity region becomes fully depleted at very low reverse voltage levels. Current flow will rapidly increase as the high resistivity region is “punched through” by impurity carriers flowing in response to the relatively low reverse bias voltage. The operation of punch-through diodes is described in the above-referenced patents in greater detail.
Integrated circuits having integral features providing ESD protection are known. One example is U.S. Pat. No. 5,426,323 to Reczek et al., entitled: “Integrated Semiconductor Circuit with ESD Protection. In the approach in the '323 patent, each integrated protection circuit included a field oxide transistor, a field-controlled diode and a diffusion resistor. Another example is provided by U.S. Pat. No. 6,239,958 to Kato et al., entitled: “Electrostatic Damage Protection Circuit and Dynamic Random Access Memory.” The approach disclosed in the '958 patent was to provide depletion mode NMOS or N-channel junction FET transistors to act as resistors during power-off mode of the integrated circuit and bypass voltage surges to a voltage supply bus. During normal powered operation, the FETs became completely depleted and presented very high impedances between the source and drain of an input transistor stage being protected.
Static induction transistors (“SIT”) are known in the art. SITs are short channel junction FETs in which the current, flowing vertically between source and drain regions, is controlled by the height of an electrostatically induced potential barrier under the source. The majority carriers in a SIT travel at saturated velocity, making high frequency operation possible in a semiconductor structure that also permits very high bias potentials. SITs also manifest relatively low capacitance between the source and drain regions. See, “High Performance Microwave Static Induction Transistors”, co-inventor A. Cogan et al., Proc, IDE'83, IEEE, pp 221–224, for example. Co-inventor A. Cogan is also listed as inventor or co-inventor on inter alia the following U.S. patents relating to SIT: U.S. Pat. Nos. 5,648,664; 5,321,283; 4,845,051; 4,751,556; 4,692,780; 4,476,622; and 4,375,124, the disclosures thereof being incorporated herein by reference thereto.
Devices that are very similar in structure if not in function to static induction transistors are known in the art as three-terminal “field controlled diode structures” (“FCDS”). One example of a field controlled diode is presented in U.S. Pat. No. 4,037,245 to Ferro, entitled: “Electric Field Controlled Diode with a Current Controlling Surface Grid”. A FCDS typically includes a uniform anode (minority carrier injection and majority carrier collection) region formed in one major surface of the substrate and a current controlling grid (gate array) at or extending from the other major surface. Interstices of the gate array include cathode regions of high injection efficiency for majority carriers. When a zero bias potential is present at the gate, significant electrical current flows between cathode and anode electrodes. A negative electric bias potential imposed at the gate causes a depletion region to form rapidly around the cathode region and pinch off the unidirectional current flow between anode and cathode. Three-terminal field controlled diodes are said to be able to control unidirectional current flows in magnitudes of up to 1000 Amperes with relatively low gate current flow. A three-terminal field controlled thyristor is proposed by U.S. Pat. No. 5,387,805 to Metzler et al., entitled: “Field Controlled Thyristor”.
A hitherto unsolved need has remained for a two-terminal barrier controlled TVS semiconductor diode that provides a factory-set clamping voltage, desirable I-V characteristics, and low capacitance, and that remains simple in design and can be produced at relative low cost.